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ltc1099 1 descriptio u features the ltc ? 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter (a/d). an internal sample- and-hold (s/h) allows the a/d to convert inputs up to the full nyquist limit. with a conversion rate of 2.5 m s, this allows 156khz 5v p-p input signals or slew rates as high as 2.5v/ m s, to be digitized without the need for an external s/h. two modes of operation, read (rd) mode and write-read (wr-rd) mode, allow easy interface with processors. all timing is internal and edge sensitive which eliminates the need for external pulse shaping circuits. the stand-alone (sa) mode is convenient for those applications not involv- ing a processor. data outputs are latched with three-state control to allow easy interface to a processor data bus or i/o port. an overflow output (ofl) is provided to allow cascading for higher resolution. n resolution: 8-bits n conversion time: 2.5 m s (rd mode) 2.5 m s (wr/rd mode) n slew rate limit (internal s/h): 2.5v/ m s n low power: 75mw max n total unadjusted error ltc1099: 1 lsb ltc1099a: 0.75 lsb , ltc and lt are registered trademarks of linear technology corporation. n built-in sample-and-hold n no missing codes n no user trims required n all timing inputs edge sensitive for easy processor interface n fast conversion time: 2.5 m s n latched three-state outputs n single 5v operation n no external clock n overflow output allows cascading n t c input allows user adjustable conversion time n 0.3" wide 20-pin pdip high speed 8-bit a/d converter with built-in sample-and-hold input frequency (khz) 1 signal-to-noise ratio, snr (db) ?6 ?8 ?0 ?2 ?4 ?6 ?8 ?0 ?2 10 100 1099 g08 t a = 25 c t c = 2.5 s infinite hold time sample-and-hold (t acq = 240ns) signal-to-noise ratio (snr) vs input frequency key specificatio s u typical applicatio n u 17 16 15 14 5 4 3 2 db7 db6 db5 db4 db3 db2 db1 db0 b1 b2 b3 b4 b5 b6 b7 b8 ltc1099 1 2 3 4 5 6 7 8 ref + ref v + v i o i o + sample hold v in v in mode wr/rdy rd cs gnd ref v cc ref + 7 1 6 8 13 10 15 17 14 18 19 3 2 7 6 4 11 12 20 20 10k 10k 2.5k 15v ?5v 5v v out lt1022 am6012 1099 ta01
ltc1099 2 co n verter characteristics u supply voltage (v cc ) to gnd voltage ...................... 12v analog and reference inputs... C 0.3v to (v cc + 0.3v) digital inputs .........................................C 0.3v to 12v digital outputs ........................ C 0.3v to (v cc + 0.3v) power dissipation .............................................. 500mw order part number ltc1099cn ltc1099acn ltc1099ain absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) v in db0 db1 db2 db3 wr/rdy mode rd int gnd 1 2 3 4 5 6 7 8 9 10 top view sw package 20-lead plastic so 20 19 18 17 16 15 14 13 12 11 v cc tc ofl db7 db6 db5 db4 cs ref + ref t jmax = 150 c, q ja = 100 c/w order part number t jmax = 150 c, q ja = 130 c/w operating temperature range ltc1099c/ltc1099ac ............................ 0 c to 70 c ltc1099i/ltc1099ai ..........................C40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, ref + = 5v, ref C = 0v and t a = t min to t max unless otherwise noted. LTC1099CSW 1 2 3 4 5 6 7 8 9 10 top view n package 20-lead pdip 20 19 18 17 16 15 14 13 12 11 v in db0 db1 db2 db3 wr/rdy mode rd int gnd v cc t c ofl db7 db6 db5 db4 cs ref + ref ltc1099ai/ltc1099i ltc1099ac/ltc1099c parameter conditions min typ max min typ max units accuracy total unadjusted error (note 3) ltc1099a l 0.75 0.75 lsb ltc1099 l 1 1 lsb minimum resolution (no missing codes) l 8 8 bits reference input input resistance l 1 3.2 6 2 3.2 4.5 k w ref + input voltage range (note 4) l ref C v cc ref C v cc v ref C input voltage range (note 4) l gnd ref + gnd ref + v analog input input voltage range l gnd v cc gnd v cc v input leakage current cs = v cc , v in = v cc , gnd l 3 3 m a input capacitance 60 60 pf sample-and-hold acquisition time 240 240 ns aperture time 110 110 ns tracking rate 2.5 2.5 v/ m s consult factory for parts specified with wider operating temperature ranges.
ltc1099 3 digital a n d dc electrical characteristics u ltc1099ai/ltc1099i ltc1099ac/ltc1099c symbol parameter conditions min typ max min typ max units v ih high level input voltage all digital inputs, v cc = 5.25v l 2.0 2.0 v v il low level input voltage all digital inputs, v cc = 4.75v l 0.8 0.0001 0.8 v i ih high level input current v ih = 5v; cs, rd, mode l 0.0001 1 1 m a v ih = 5v; wr l 0.0005 3 0.0005 3 m a i il low level input current v il = 0v; all digital inputs l C0.0001 C1 C0.0001 C1 m a v oh high level output voltage db0-db7, ofl, int; v cc = 4.75v i out = 360 m a l 2.4 4.0 2.4 4.0 v i out =10 m a 4.7 4.7 v v ol low level output voltage db0-db7, ofl, int, rdy; v cc = 4.75v i out =1.6ma l 0.4 0.4 v i oz hi-z output leakage db0-db7, rdy; v out = 5v l 0.1 3 0.1 3 m a db0-db7, rdy; v out = 0v l C0.1 C3 C0.1 C3 m a i source output source current db0-db7, ofl, int; v out = 0v l C11 C6 C11 C7 ma i sink output sink current db0-db7, ofl, int, rdy; v out = 5v l 14 7 14 9 ma i cc supply current cs = wr = rd = v cc l 11 20 11 15 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, ref + = 5v, ref C = 0v and t a = t min to t max unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, ref + = 5v, ref C = 0v and t a = t min to t max unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltages are with respect to gnd (pin 10) unless otherwise noted. ac characteristics note 3: total unadjusted error includes offset, gain, linearity and hold step errors. note 4: reference input voltage range is guaranteed but is not tested. ltc1099ai/ltc1099i ltc1099ac/ltc1099c symbol parameter conditions min typ max min typ max units rd mode (figure 2) pin 7 = gnd t crd conversion time t a = 25 c 2.2 2.5 2.8 2.2 2.5 2.8 m s l 5.0 3.75 m s t rdy delay from cs to rdy c l = 100pf 70 70 ns t acc0 delay from rd to output data valid c l = 100pf t crd + 35 t crd + 35 ns t inth delay from rd - to int - c l = 100pf 70 70 ns t 1h , t 0h delay from rd - to hi-z state on outputs test circuit figure 1 70 70 ns t p delay time between conversions 700 700 ns t acc2 delay time from rd to output data valid 70 70 ns wr/rd mode (figures 3 and 4) pin 7 = v cc t cwr conversion time t a = 25 c 2.2 2.5 2.8 2.2 2.5 2.8 m s l 5.0 3.75 m s t acc0 delay time from wr to output data valid c l = 100pf t cwr + 40 t cwr + 40 ns t acc2 delay from rd to output data valid c l = 100pf 70 70 ns t inth delay from rd - to int - c l = 100pf 70 70 ns t ihwr delay from wr to int - c l = 100pf 240 240 ns t 1h , t 0h delay from rd - to hi-z state on outputs test circuit figure 1 70 70 ns t p delay time between conversions 700 700 ns t wr minimum wr pulse width 55 55 ns
ltc1099 4 ambient temperature, t a ( c) ?0 conversion time/conversion time at 25 c conversion time ( s) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 4.5 4.0 3.5 3.0 2.5 2.0 1.5 25 75 1099 g07 ?5 0 50 100 125 input frequency (khz) 1 signal-to-noise ratio, snr (db) ?6 ?8 ?0 ?2 ?4 ?6 ?8 ?0 ?2 10 100 1099 g08 t a = 25 c t c = 2.5 s conversion time vs temperature signal-to-noise ratio (snr) vs input frequency typical perfor a ce characteristics uw ambient temperature, t a ( c) 20 18 16 14 12 10 8 6 4 2 0 supply current, i cc (ma) 1099 g01 50 25 0 25 50 75 100 125 reference voltage, v ref (v) 0 v os error (lsb) 2 4 5 4 3 2 1 0 1099 g02 13 t a = 25 c t c = 2.5 s v os error vs reference voltage linearity error vs reference voltage supply current vs temperature reference voltage, v ref (v) 0 linearity error (lbs) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 4 1099 g03 1 2 3 5 t a = 25 c t c = 2.5 s 1099 g04 reference voltage, v ref (v) 0 total error (lsb) 2 4 5 4 3 2 1 0 13 t a = 25 c t c = 2.5 s resistance (k ) 10 conversion time ( s) 100 10 1.0 0.1 100 1000 1099 g05 resistor between pin 19 and v cc resistor between pin 19 and gnd t a = 25 c conversion time ( s) 1.6 0 total unadjusted error (lbs) 0.2 0.6 0.8 1.0 1.8 2.0 2.1 2.5 1099 g06 0.4 1.7 1.9 2.2 2.3 2.4 t a = 25 c total error vs reference voltage conversion time vs r ext accuracy vs conversion time
ltc1099 5 pi n fu n ctio n s uuu v in (pin 1): analog input. db0 to db3 (pins 2 to 5): data outputs. db0 = lsb. wr/rdy (pin 6): wr/rdy is an input when m0de = v cc . falling edge of wr switches internal s/h to hold then starts conversion. wr/rdy is an open drain output (active pull-down) when m0de = gnd. rdy goes low at start of conversion and pull-down is turned off when conversion is complete. resistive pull-up is usually used in this mode. mode (pin 7): wr-rd when mode = v cc . rd when m0de = gnd. no internal pull-down. rd (pin 8): a low on rd with cs low activates three- state outputs. with mode = gnd and cs low, the falling edge of rd switches internal s/h to hold and starts conversion. int (pin 9): output that goes low when the conversion in process is complete and goes high after data is read. gnd (pin 10): ground connection. ref C (pin 11): low reference potential (analog ground). ref + (pin 12): high reference potential. v ref = full scale = (ref + ) C (ref C ). cs (pin 13): chip select. when high, data outputs are high impedance and all inputs are ignored. db4 to db7 (pins 14 to 17): data outputs. db7 = msb. ofl (pin 18): overflow output. goes low when v in > v ref . t c (pin 19): user adjustable conversion time. v cc (pin 20): positive supply. 4.75v v cc 5.25v. test circuits rd rd cs c l data out v cc v cc 1k rd cs c l data out v cc v cc t 1h t r = 20ns, c l = 10pf t 0h t r = 20ns, c l = 10pf gnd rd v cc gnd gnd v 0h data out v cc v 0l data out t r t r t 1h t 0h 90% 90% 90% 50% 50% 10% 10% 10% 1099 f01 1k figure 1. three-state test circuit
ltc1099 6 cs wr/rdy db0-db7 int rd old data new data t p t cwr t acc0 t acc2 t 1h , t 0h t inth 1099 f03b old data new data t p t cwr t acc0 t ihwr cs (gnd) rd (gnd) db0-db7 int wr/rdy 1099 f04 figure 3a. wr-rd mode (pin 7 is high and t rd > t cwr ) figure 3b. wr-rd mode (pin 7 is high and t rd < t cwr ) figure 4. wr-rd mode (pin 7 is high) standalone operation cs wr/rdy db0-db7 int rd t p t cwr t 1h , t 0h t acc2 t inth 1099 f03a ti i g diagra s u w w cs rd db0-db7 int wr/rdy old data new data t p t rdy t crd t acc0 t 1h , t 0h t acc2 t inth 1099 f02 figure 2. rd mode (pin 7 is gnd)
ltc1099 7 fu n ctio n al descriptio uu u figure 5 shows the functional block diagram for the ltc1099 2-step flash adc. it consists of two 4-bit flash converters, a 4-bit dac and a differencing circuit. the conversion process proceeds as follows: 1. at the start of the conversion, the on-board sample- and-hold switches from the sample to the hold mode. this is a true sample-and-hold with an acquisition time of 240ns, an aperture time of 110ns and a tracking rate of 2.5v/ m s. 2. the held input voltage is converted by the 4-bit ms- flash adc. this generates the upper or most significant 4-bits of the 8-bit output. 3. a 4-bit approximation, from the dac output, is sub- tracted from the held input voltage. 4. the ls-flash adc converts the difference between the held input voltage and the dac approximation. this generates the lower or least significant (ls) 4-bits of the 8-bit output. the ls-flash reference is one six- teenth of the ms-flash reference. this effectively mul- tiplies the difference by 16. 5. upon the completion of the ls 4-bit flash the eight output latches are updated simultaneously. at the same time, the sample-and-hold is switched from the hold mode to the acquire mode in preparation for the next conversion. the advantage of this approach is the reduction in the amount of hardware required. a full flash converter re- quires 255 comparators while this approach requires only 31. the price paid for this reduction in hardware is an increase in conversion time. a full flash converter requires only one comparison cycle while this approach requires two comparison cycles, hence 2-step flash. this architecture is further simplified in the ltc1099 by reusing the ms-flash hardware to do the ls-flash. this reduces the number of comparators from 31 to 16. this is possible because the ms and ls conversions are done at different times. to take the simple block diagram of figure 5 and reconfigure it to reuse the ms-flash to do the ls-flash is conceptually simple, but from a hardware point of view is not practical. a new six input switched capacitor comparator is used to + ls 4-bit flash ms 4-bit flash 4-bit dac v ref /16 v in v ref b7 b6 b5 b4 b3 b2 b1 b0 1099 f05 remainder accomplish this function in a simple, although not straight forward, manner. figure 6 shows the six input switched capacitor compara- tor. intuitively, the comparator is easy to understand by noting that the common connection between the two input capacitors, c1 and c2, acts like a virtual ground. in operational amplifier circuits, current is summed at the virtual ground node. input voltage is converted to current by the input resistors. in the switched capacitor compara- tor, input voltage is converted to charge by the input capacitors and these charges are summed at the virtual ground node. a major advantage of this technique is that the switch-on impedance has no affect on accuracy as long as sufficient time exists to fully charge and discharge the capacitors. during the first time period the t+ and t z switches are closed. this forces the common node between c1 and c2 to an arbitrary bias voltage. since the capacitors subtract out this voltage, it may be considered, for the sake of this discussion, to be exactly zero (i.e., virtual ground). note figure 5. 8-bit 2-step semiflash a/d
ltc1099 8 hold t z t+ t ? t ? t z t z t+ t ? t ? strobe sample sample (+) (+) (? (? (? (? v in ms tap dac 0.5 lsb 0v ls tap c2 c1 virtual ground c1 = c2 1099 f06 fu n ctio n al descriptio uu u also that variations in the bias voltage with time and temperature will also be rejected. in this state, c1 charges to v in . when t z opens, v in is held on c1. the next step is the first comparison the ms-flash. t z and t+ are opened and t C1 is closed. the equation for each comparator is: v in + 0.5lsb C ms tap = 0v there are 16 identical comparators each tied to the tap on a 16 resistor ladder. the ms tap voltages vary from v ref to 0v in 16 equal steps of v ref /16. notice that capacitor c2 adds 0.5lsb to v in . this offsets the converter transfer function by 0.5lsb, equally distrib- uting the 1lsb quantization error to 0.5lsb. the outputs of the 16 comparators are temporarily latched and drive the 4-bit dac directly without need of decoding. this holds the dac output constant for the next step the ls conversion. the ls conversion is started when t C1 is opened and t C2 is closed. capacitor c1 subtracts the 4-bit dac approximation from v in and inputs the difference charge to the virtual ground node. the equation for each comparator is: v in + 0.5lsb C v dac C ls tap = 0v the 4-bit dac approximation is input to all 16 compara- tors. the ls tap voltages are converted to charge by capacitor c2. ls taps vary from v ref /16v to 0v in 16 equal steps of v ref /256. the comparators look at the net charge on the virtual ground node to perform the ls-flash con- version. when this conversion is complete, the four lsbs along with the four msbs are transferred to the output latches. in this way, all eight outputs will change simultaneously. figure 6. six input switched capacitor comparator
ltc1099 9 when rd goes low, with cs low, the result of the previous conversion is output. this data stays there until the ongoing conversion is complete (int goes low). at this time the outputs are updated with new data. as long as cs and rd stay low long enough, the receiving device will get the right data. remember, the receiving device reads data in on the rising edge of rd. the rdy output facilitates making rd long enough. in the rd mode, the wr input becomes the rdy output. on the falling edge of rd, the rdy goes low. it is an open drain output to allow a wired or function so it requires a pull-up resistor. at the end of conversion, the active pull- down is released and rdy goes high. the rdy output is designed to interface to the ready in (rdyin) function on many popular processors. rdyin allows these processors to work with slow memory by stretching the rd strobe coming from the processor. rd will remain low as long as rdy is low. in the case of the ltc1099, rdy stays low until the conversion is complete and new data is available on the outputs. this greatly simplifies the programmers task. each time data is re- quired from the a/d a simple read is executed. the hardware interface makes sure the rd strobe is long enough. adjusting the conversion time the conversion time of the ltc1099 is internally set at 2.5 m s. if desired, it can be adjusted by forcing a voltage on pin 19. with pin 19 left open, the conversion time runs 2.5 m s. a convenient way to force the voltage is with the circuit shown in figure 7. to preset the conversion time to a fixed amount, a resistor may be tied from pin 19 to v cc or gnd. tying it to v cc slows down the conversion and tying it to gnd will speed it up (see typical performance characteristics). digital i u terface the digital interface to the ltc1099 entails either control- ling the conversion timing or reading data. there are two basic modes for controlling and reading the a/d the write-read(wr-rd) mode and the read (rd) mode. wr-rd mode (pin 7 = high) in the wr-rd mode, a conversion sequence starts on the falling edge of wr with cs low (figures 3a and 3b). this is an edge-sensitive control function. the width of the wr input is not important. all timing functions are internal to the a/d. the first thing to happen after the falling edge of wr is the internal s/h is switched to hold. this typically takes 110ns after wr falls and is the aperture time of the s/h. next, the a/d conversion takes place. the conversion time is internally set at 2.5 m s, but is user adjustable (see adjusting the conversion time). the end of conversion is signaled by the high to low transition of int. the s/h is switched back to the acquire state as soon as the conver- sion is complete. after the conversion is complete, the 8-bit result is avail- able on the three-state outputs. the outputs are active with rd and cs low. output data is latched and, if no new conversion is initiated, is available indefinitely as long as the power is not turned off. the wr-rd mode is also used for stand-alone operation. by tying cs and rd low the data outputs will be continu- ously active (figure 4). the falling edge of wr starts the conversion sequence and when done new data will appear on the outputs. all outputs will be updated simultaneously. in stand-alone operation, the outputs will never be in a high impedance state. rd mode (pin 7 = low) in the rd mode, a conversion sequence is initiated by the falling edge of rd when cs is low (figure 2). the s/h is switched to the hold state 110ns after the falling edge of rd. it is switched back to the acquire state at the end of conversion. 1 2 20 19 5v 10k 1099 f07 figure 7. adjusting the conversion time
ltc1099 10 a n alog i n terface uu the inclusion of a high quality sample-and-hold (s/h) simplifies the analog interface to the ltc1099. all of the error terms normally associated with an s/h (hold step, offset, gain and droop errors) are included in the error specifications for the a/d. this makes it easy for the designer since all the error terms need not be taken into account individually. s/h timing a falling edge on the rd or wr input switches the s/h from acquire to hold and starts the conversion. the aperture time is the delay from the falling edge to the actual instant when the s/h switches to hold. it is typically 110ns. as soon as a conversion is complete (2.5 m s typ), the s/h switches back to the sample mode. even though the acquisition time is only 240ns, a new conversion cannot be started for (700ns typ) after a conversion is completed. analog input the input to the a/d looks like a 60pf capacitor in series with 550 w (figure 8). with this high input capacitance care must be taken when driving the inputs from a source amplifier. when the input switch closes, an instantaneous capacitive load is applied to the amplifier output. this acts like an impulse into the amplifier and if it has poor phase margin the resulting ringing can cause a considerable loss of accuracy. if the amplifier is too slow the resulting settling tail will also cause a loss of accuracy. the amplifier should also have low open circuit output impedance. the lt1006 is an 1099 f08 v in 550 to a/d 60pf figure 8. equivalent input circuit excellent amplifier in this regard. it also works with a single supply which fits nicely with the ltc1099. reference inputs sixteen equal valued resistors are internally connected between ref + and ref C . each resistor is nominally 200 w giving a total resistance of 3.2k between the reference terminals. when v in equals ref + , the output code will be all ones. when v in equals ref C , the output code will be all zeros. although it is most common to connect ref + to a 5v reference and ref C to ground, any voltages can be used. the only restrictions are ref + >ref C and ref + and ref C must be within the supply rails. as the reference voltage is reduced the a/d will eventually lose accuracy. accuracy is quite good for references down to 1v. even though the reference drives a resistive ladder, a lot of capacitive switching is taking place internally. for this reason, driving the reference has the same characteristics as driving v in . a fast low impedance source is necessary. the reference has the additional problem of presenting a dc load to the driving source. this requires the dc as well as the ac source impedance to be low. good grounding as with any precise analog system care must be taken to follow good grounding practices when using the ltc1099. the most noise free environment is obtained by using a ground plane with gnd (pin 10) and ref C (pin 11) tied to it. bypass capacitors from ref + (pin 12) and v cc (pin 20) with short leads are also required to prevent spurious switching noise from affecting the conversion accuracy. if a ground plane is not practical, single point grounding techniques should be used. ground for the a/d should not be mixed in with other noisy grounds.
ltc1099 11 a n alog i n terface uu applications analog multiplier the schematic figure 9 shows the ltc1099 configured with a dac to form a two quadrant analog multiplier. an input waveform is applied to the ltc1099 where it is digitized at a 300khz rate. the digitized signal is fed to the dac in flow-through mode where another signal is input to the dac reference input. in this way, the two analog signals are multiplied to produce a double sideband ampli- tude modulated output. figure 10 shows a 3khz sine wave multiplied by a 100hz triangle. + 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 14 13 12 11 10 9 8 20 19 18 17 16 15 14 13 12 11 24 23 22 21 20 19 18 17 16 15 14 13 n/c n/c n/c clk 3mhz osc 5v 5v out 74ls90 lt1019-5 10 = 300khz = analog ground = digital ground 15v in 5v ref agnd 25k out trim gnd in ltc1099 db0 db1 db2 db3 wr/rdy mode rd int gnd cs wr1 gnd di5 di4 di3 di2 di1 di0 v ref rfb v cc wr2 xfer di6 di7 di8 di9 di10 di11 i out2 i out1 db7 db6 db5 db4 cs ref + ref byte 1/ byte 2 (v in1 ) 0v to 5v analog input (v in2 ) +10v to ?0v analog input cs and rd low 4 db0-db3 4 db4-db7 88 microlinear mp1208 dac 12v 10 f 4.7 f 0.01 f 10 f 50k offset null 15v ?5v 15v 10pf 1 5 lt1056 5v figure 9 note that since this is only a two quadrant multiplier, a carrier component (the input to the ltc1099) will appear in the output spectrum. figure 11 shows the frequency spectrum of a 42.5khz sine wave multiplied by a 5khz sine wave. the depth of modulation is about 30db. figure 12 shows a 42.375khz sine wave multiplied by a 30.875khz sine wave. note that at these higher frequencies, the depth of modulation is still about 30db. the carrier feed-through is seen in figure 12. v in1 @ 0v to 5v triangle into ltc1099 ~100hz v in2 @ 4.8v sine into dac ~ 3khz 1099 f10 figure 10
ltc1099 12 0 ?0 10dbv/div 32.5 34.5 36.5 38.5 40.5 42.5 44.5 46.5 48.5 50.5 52.5 37500hz 42500hz 47500hz 1099 f11 0 ?0 10dbv/div 5 152535455565758595105 30875hz 11500hz 42375hz 73250hz 1099 f12 figure 11. two quadrant multiplier output spectrum with 0v to 4.5v at 42.5khz into ltc1099 and 2v at 5khz into dac figure 12. two quadrant multiplier output spectrum with 0v to 4.5v at 42.375khz into ltc1099 and 2v at 30.875khz into dac a n alog i n terface uu
ltc1099 13 typical applicatio n s u 0001 0000 0002 0032 aorg >32 0003 0032 ce01 dint disable interrupts 0004 0033 c800 ldpk >00 data page pointer is 0 0005 0034 8064 loop in 100,pao input 1099 data to address 100 0006 0035 cb13 rptk 12 repeat next instruction 12 times 0007 0036 5500 nop dont convert again too soon 0008 0037 ff80 b loop go for another conversion tms320c25 assembly code for rd mode interface to ltc1099 v in db0 db1 db2 db3 wr/rdy mode rd int gnd v cc tc ofl db7 db6 db5 db4 cs ref + ref v cc y0 y1 y2 y3 y4 y5 y6 a0 a1 a2 is a3 d4 d5 d6 d7 d0 d1 d2 d3 a b c g2a g2b g1 y7 gnd 5v c1 c2 c1 c2 ltc1099 + + 10k 5v 5v (6) (b8) (c10) (h10) (4) (5) (3) (1) (2) ready msc strb v ss v cc tms320c25 (b1, k11, l2) (a10, b11, h2, l6) (k1) (k2) (l3) (j11) (k3) (d1) (c2) (c1) (b2) (f1) (e2) (e1) (d2) analog input voltage 1/2 74as00 5v 1099 ta03 c1 = 4.7 f tantalum c2 = 0.1 f ceramic 74as138 tms320c25 interface using rd mode
ltc1099 14 typical applicatio n s u 0001 0032 aorg >32 0002 0032 ce01 dint disable interrupts 0003 0033 c800 ldpk >0 data page pointer is 0 0004 0034 e064 loop out >64.pao start ltc1099 conversion 0005 0035 cb20 rptk >12 wait for conversion to finish 0006 0036 5500 nop 0007 0037 8064 in >64.pao read ltc1099 data; store in >64 0008 0038 ff80 b loop do again tms320c25 assembly code for wr/rd mode interface to ltc1099 tms320c25 interface using wr/rd mode v in db0 db1 db2 db3 wr/rdy mode rd int gnd v cc t c ofl db7 db6 db5 db4 cs ref + ref v cc y0 y1 y2 y3 y4 y5 y6 in1 in1 out1 in2 1n2 out2 gnd v cc in4 in4 out4 in3 in3 out3 5v c1 c2 c3 c4 ltc1099 + + c6 c7 + 5v c8 0.1 f 5v 5v 5v 5v (b8) (c10) (h10) (h11) ready msc strb r/ w v ss v cc tms320c25 (a10, b11, h2, l6) (k1) (k2) (l3) (j11) (k3) (f1) (e2) (e1) (d2) analog input voltage 1099 ta04 c1, c3, c6 = 4.7 f tantalum c2, c4, c5, c7, c8 = 0.1 f ceramic 74f00 a0 a1 a2 is a3 d0 d1 d2 d3 74f138 c5 0.1 f d7(b2) d6(c1) d5(c2) d4(d1) a b c g2a g2b g1 y7 gnd
ltc1099 15 package descriptio u dimensions in inches (millimeters) unless otherwise noted. n20 1098 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 (2.54) bsc 0.255 0.015* (6.477 0.381) 1.040* (26.416) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n package 20-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) s20 (wide) 1098 note 1 0.496 ?0.512* (12.598 ?13.005) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) bsc 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** sw package 20-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc1099 16 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments ltc1274/ltc1277 12-bit, 100ksps parallel/2-byte adc 5v or 5v, 10mw with 1 m a shutdown ltc1279 12-bit, 600ksps parallel adc 5v, 60mw, 70db sinad ltc1406 8-bit, 20msps parallel adc 5v, 150mw, 48.5db sinad ltc1409 12-bit, 800ksps parallel adc 5v, 80mw, 72.5db sinad ltc1419 14-bit, 800ksps parallel adc 5v, 150mw, 81.5db sinad cs wr rd b0 b1 b2 b3 b4 b5 b6 b7 b8 ofl cs wr/rdy db0 db1 db2 db3 db4 db5 db6 db7 ofl p bus rd 13 8 2 3 4 5 14 15 16 17 18 6 cs wr/rdy db0 db1 db2 db3 db4 db5 db6 db7 ofl v cc v in mode v ref + v ref gnd rd 13 8 2 3 4 5 14 15 16 17 18 20 1 7 12 11 10 6 5v v in 5v 5v v cc v in mode v ref + v ref gnd 20 1 7 12 11 10 5v 5v ltc1099 ltc1099 1k 5k 1k 4.7 f 4.7 f 4.7 f 1099 ta02 cascading for 9-bit resolution typical applicatio s u ? linear technology corporation 1989 sn1099 1099fas lt/tp 1100 2k rev a ? printed in usa

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